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controllers:microsemi [2012/10/23 21:34] – created heinzcontrollers:microsemi [2018/08/21 23:09] (current) – external edit 127.0.0.1
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 +====== Microsemi ======
 +
 Try to put the latest devices on top of each section and mark end-of-line products. Only specify the main parameters of the micro controllers and go more into deep with details about the CAN interface. Always try to put a link to the data sheet or manual. Try to put the latest devices on top of each section and mark end-of-line products. Only specify the main parameters of the micro controllers and go more into deep with details about the CAN interface. Always try to put a link to the data sheet or manual.
  
 +In March 2018 Microchip Technology announced it would acquire Microsemi for approximately $10 billion.
 ===== SoC ===== ===== SoC =====
  
-**SmartFusion2** ARM Cortex-M3 Processor and Microcontroller Subsystem in SmartFusion2 SoC FPGA Devices+[[http://www.actel.com/products/smartfusion2/default.aspx | SmartFusion2]] 166 MHz ARM Cortex-M3 Processor and Microcontroller Subsystem in SmartFusion2 SoC FPGA Devices. Microsemi has announced the availability of its first production-qualified System-on-Chip FPGAs, the M2S050 and M2S050T, for June 2013. 
 + 
 +The SmartFusion2 concept is used in [[ http://www.anybus.com/ | HMS]] new flagship, the [[http://www.anybus.com/products/abcc40.shtml  | NP40]] network processor. It is used by HMS to realize standard fieldbus protocols like CAN, but also all kinds of real time Ethernet. 
 + 
 + 
 +**CAN Controller Features:**  
 + 
 +Possibly the [[controllers:inicore|Inicore]] CANmodule-IIIx is implemented. [[http://www.inicore.com/news/press_2013_canmod3x_microsemi.html | Press release]]. 
 + 
  
 Receive Path Receive Path
-  * 32 receive buffers + 
-  * Each buffer has its own message filter + 
-  * Message filter covers: ID, IDE, RTR, Data byte 1, and Data byte 2 +    * 32 receive buffers 
-  * Message buffers can be linked together to build a bigger message array. +    * Each buffer has its own message filter 
-  * Automatic remote transmission request (RTR) response handler with optional generation of RTR interrupt+    * Message filter covers: ID, IDE, RTR, Data byte 1, and Data byte 2 
 +    * Message buffers can be linked together to build a bigger message array. 
 +    * Automatic remote transmission request (RTR) response handler with optional generation of RTR interrupt 
 + 
 Transmit Path Transmit Path
-  * 32 Transmit message holding registers with programmable priority arbitration + 
-  * Message abort command + 
-  * Single-shot transmission (SST) (no automatic retransmission upon error or arbitration loss) EDAC+    * 32 Transmit message holding registers with programmable priority arbitration 
 +    * Message abort command 
 +    * Single-shot transmission (SST) (no automatic retransmission upon error or arbitration loss) EDAC 
  
 The [[http://www.actel.com/documents/SmartFusion2_CortexM3_UG.pdf|User Manual]] Chapter 11 – CAN Controller. The [[http://www.actel.com/documents/SmartFusion2_CortexM3_UG.pdf|User Manual]] Chapter 11 – CAN Controller.
  
  
-===== FPGA ======+===== FPGA =====
  
 +Microsemi (USA) has announced PCIe implementations based on [[http://www.microsemi.com/products/fpga-soc/fpga/igloo2-fpga | IGLOO2]] FPGAs. The products, which are compliant to PCI express specifications, also provide CAN connectivity. The on-chip CAN has been tested by the C&S group (Germany) according to ISO 16845 and some additional test cases.
 ===== 8 bit Controllers ===== ===== 8 bit Controllers =====
  

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