Welcome to the CAN-bus Wiki project

Differences

This shows you the differences between two versions of the page.

--- controllers:arasan [2022/07/04 11:28] – [FPGA / IP] heinz
+++ controllers:arasan [2023/10/20 18:57] (current) – [FPGA / IP] CAN-XL heinz
@@ Line 8: / Line 8: @@
 ===== FPGA / IP ======
+[[https://www.arasan.com/product/can-bus-ip/ | Overview]]
 Arasan [[https://www.arasan.com/news/arasan-announces-its-2nd-generation-of-can-ip/ | announces]] its 2’nd Generation of CAN IP on May 2022.
@@ Line 19: / Line 19: @@
 The IP can be integrated into devices that require CAN connectivity commonly used in automotive and industrial applications. The ISO 11898-2.2015 version is planned for end of 2015. The IP provides an AHB-Lite slave interface for connecting to the CPU with the option of APB and it supports a 32-bit interface.
 Provided as [[wp>Verilog]] HDL.
+[[https://www.arasan.com/product/can-xl/ | CAN XL]] supports CAN 2.0, CAN-FD & CAN-XL Specifications. Also supports original Bosch Protocol & ISO 11898 specifications for TTCAN (Time Triggered Operation) as specified in ISO11898-4.  Easy to integrate with the Host processor using the AMBA-AXI standard interface.
 Currently data sheet is available available only after registration.