Welcome to the CAN-bus Wiki project

Silvaco, Inc.

IP Cores

  • FlexCAN
    The FlexCAN core comes with a Verilog RTL source code, a test bench, and documentation. The transmit- and receive-mailboxes are configurable (0 to 8, 16, 32, or 64 byte). The receive FIFO is able to store up to 6 data frames. The time-stamping is based on a 16-bit free-running timer with an optional external time tick. The transmission of data frames can be aborted. The core features listen-only mode and CAN FD transmitter delay compensation. Additionally, it provides a detection and correction (ECC) of memory read.
    • Full implementation of CAN FD and CAN 2.0 B
      • Standard/extended data frames
      • Up to 8Mbit/s
      • 0-64 bytes data length
    • Compliant with ISO 11898-1
    • Flexible mailboxes configurable
      • To store 0-8, 16, 32, or 64 data bytes
      • As receive or transmit
    • Individual Rx mask register per mailbox
    • Full featured Rx FIFO, stores up to 6 frames
    • Transmission abort capability
    • Listen-only mode
    • Loop-back mode supporting self-test operation
    • Programmable transmission priority scheme
    • Time stamp based on 16-bit free-running timer with an optional external time tick
    • Low power modes with programmable wake-up on bus activity or matching with received frames (pretended networking)
    • Transceiver delay compensation for CAN FD Tx at faster data rates
    • Detection and correction of memory read (ECC)
    • SystemVerilog integration testbench including a number of usage scenarios

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